HONEYWELL TC-PPD011 Digital conversion module

Scan sets on the master do not work properly for the first operation of the scan set after entering RUN mode. They do work properly for subsequent scans. After downloading a new hardware configuration and logic, a power cycle may be required to resume FANUC I/O operation. Use PLCs of similar performance in FANUC I/O networks. If a master or slave is located in an RX3i system, the other PLCs should be RX3i CPUs or Series 90-30 CPU374s. Repeated power up/down cycles of an expansion rack containing FANUC I/O slaves may result in failure of the slaves’ operation, with the RDY LED off. Lost count at power up for Serial IO Processor The serial IO Processor (IC693APU305) will lose the first count after every power up or every time the module receives a configuration.

In previous releases

the CPU allowed configuration of COMMREQ Status Words in bit memory types on a non-byte-aligned boundary. Even though the given reference was not byte-aligned, the firmware would adjust it the next-lowest byte boundary before updating status bits, overwriting the bits between the alignment boundary and specified location. To ensure that the application operates as expected, release 3.50 requires configuration of COMMREQ Status Words in bit memory types to be byte-aligned. For example if the user specified status bit location of %I3, the CPU aligns the status bit location at %I1. Release 3.50 firmware requires the user to specify the appropriate aligned address (%I1) to ensure that the utilized location is appropriate for their application. Note that the actual reference location utilized is not changed, but now is explicitly stated for the user.

STOP and RUN mode transition priority

The PACSystems CPU receives requests to change between stop and run mode from many different sources. These include (but are not limited to) Proficy Machine Edition, HMIs, the user application, and the RUN/STOP switch. Since there are many potential sources for a mode change request, it is possible to receive a new mode change request while another is already in progress. When this occurs, the CPU evaluates the priority of the new mode change request with the mode change that is in progress. If the new mode change request has an equal or higher priority than the one already in progress, the CPU transitions to the new mode instead of the one in progress. If, however, the new mode change request has a lower priority than the one in progress, the new mode request is discarded and the CPU completes the mode change that is in progress. The sweep mode priorities are (listed from highest to lowest priority) STOP HALT, STOP FAULT, STOP, and RUN. (Note: The IO ENABLED/DISABLED state is not part of the mode priority evaluation.)

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