• RESET/ABORT key
• Reset watchdog timer
• Status LEDs
• Rotary switches
• Three 16-bit timers with prescaler in each of the two CIO Z8536 devices. Two timers are cascadable.
• One 8-bit timer with software programmable clock (FGA-002).
• All local I/O devices are able to interrupt the local CPU on a software programmable level.
• Bus timeout counters for local and APN accesses.
• VMEPROM, the real time monitor with file manager and real time kernel (PDOS compatible) is installed on each board version.
Differences in the -501 Variant
The differences between the SYS68K/CPU-30SEN-R-501 board and the standard CPU-30SEN-R board are listed below.
• new PCB formfactor (Ericsson ROJ207, described in 1057-TVJ 807+ Ux and 1077-TVJ 807+ Ux)
• onboard DC/DC power supply (-48V to +5V) with solid state fuse on input. CPU board main supply voltage is only -48V.
• improved ESD/EMC properties (fulfills the requirements of BYB501 Ericsson equipment practice) • metric backplane connectors for backplane interfacing instead of two VG96 connectors.
• 12-pin front panel connector for reset removed and 12-pin front panel connector for RS-232 channel 2 now changed to 9-pin D-Sub connector
• front panel switches for RESET and ABORT accessible only through an extraction hole to prevent accidental switching
Additional features
The additional features of the SYS68K/CPU-30SEN-R-501 board are listed below.
• isolated I2 C bus accessible from backplane connector even when board is not powered on
• serial EEPROM 256-byte (for board ID-data) and I2C serial to parallel I/O device (as diagnostic I2C LED driver) are connected to I2Cbus
• hot insertion capability (board can be inserted and removed without switching off the power supply)
• metric backplane connectors with leading pins for early GND connection for hot insertion/removal support are needed
• BYB501 equipment practice specific board coding functions
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