ABB 3BHE009681R0101 CVC750BE101 Thyristor module

This CPU board is a high performance single-board computer providing an A24/D16 APNbus interface including DMA. It is based on • the 68030 CPU, • the FORCE gate array FGA-002, • and the APNbus. Memory The CPU-30SEN-R provides up to 32 MByte shared DRAM on-board, up to 8 MByte system flash memory, and up to 256 KByte SRAM with on-board battery backup. The shared DRAM is accessible from the 68030 CPU, the FGA-002 DMA controller, and also from the other APNbus masters.

The CPU-30SEN-R has two RS-232 

serial I/O ports at the front panel permitting a console port for download and data communication. The single-ended SCSI interface is available via the 3-row APNbus connectors JACK 1/JACK 3. Additional interface logic implemented in the APN LCA adapts the FGA-002 VMEbus interface to the Ericsson APNbus interface (APNbus Specification 1/155 19 - APN 167 01 Uen). CPU speed The CPU-30SEN-R runs at 25 MHz. Real-time clock A real-time clock with battery backup is also available.

Hardware Interface of the 68030 

The 68030 microprocessor uses a nonmultiplexed address and data bus. Asynchronous signals allow easy interfacing to the outside world; synchronous signals perform fast interaction. The CPU drives the address signals (A0-A31), the size signals (SIZ0, SIZ1) and the function code signals (FC0-FC2) on every cycle, independent of a cache hit or miss. These signals are used to decode the memory map of the CPU board. The hardware on the CPU board is notified by the address and data strobe signals that the current cycle is not a cache cycle, and that the decoding outputs are strobed to be valid.

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