The access address of the Shared DRAM from the APNbus is also programmable via FGA-002. That is the address range that other APNbus masters must use in order to access the Shared DRAM on the CPU board. This is not necessarily the same address range used by the CPU for local accesses. As APNbus is limited to A24-addressing which opens 16MB of accessible address space on the 32MB DRAM variants special techniques are necessary to access the whole DRAM. Please see “APNbus Slave Interface” on page 116 for more information.
Shared DRAM Performance
The memory interface logic controlling the Shared DRAM array is optimized for fast accesses from the 68030 microprocessor, providing the highest possible performance. Because the 68030 microprocessor contains an on-chip data and instruction cache, many CPU accesses are cache line "burst fills". These burst transactions attempt to read 16 consecutive bytes into the 68030, using four 4-byte cycles. The first read cycle of such a burst usually requires 4 CPU clock cycles (160 nanoseconds at 25 MHz). Due to the optimized design of the memory control logic, each subsequent cycle only requires 1 CPU clock cycle (40 nanoseconds) to complete. This is commonly called a "4-1-1-1" burst transfer. Overall, the total cache line "burst fill" operation requires 7 clock cycles to transfer 16 bytes, providing a memory bandwidth of over 50 MBytes/second.
The System Flash Memory
The System Flash Memory consists of 4 flash memory devices (Surface Mount Devices).
Not all CPU accesses are burst transfers. Single read and write transactions are also supported at the fastest possible speed. A single read or write access (1, 2, or 4 bytes) requires 4 CPU clock cycles. Distributed asynchronous refresh is provided every 15 microseconds. An access during a pending refresh cycle may be delayed by a maximum of four additional clock cycles.
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