ABB 3HAB8101-8/08Y Processing module

The first two read cycles after reset of the microprocessor are operand fetches of the Initial Interrupt Stack Pointer (ISP) and the Initial Program Counter (IPC). These operands are always fetched from addresses 0000.000016 and 0000.000416, respectively. Special control logic in FGA-002 maps the Boot Flash memory (not the System Flash Memory) down to the ISP and IPC address to allow the 68030 to boot from a single byte-wide Boot Flash memory device. This facilitates debugging and low-level program development. However, when the initialization routines in the Boot Flash memory device are completed, control is transferred to the System Flash Memory in such a way that the 68030 appears to have been booted from the System Flash Memory, not the Boot Flash memory.

Memory Organization of the System Flash Memory 

The data path of the System Flash Memory is 32-bit wide, separated into four byte paths. Each byte path is connected to one Flash Memory device. 5.3.3 Read/Write to the System Flash Memory Read cycles with any port size are allowed. Write cycles are flagged by the FGA-002 Gate Array with BERR. A programmable bit within the FGA-002 may be used to enable write operation to the System Flash Memory. In this case the FGA-002 will respond with an asynchronous data acknowledge (DSACK0, DSACK1). The write affects the System Flash Memory depending on switch SW6-3.

Programming the System Flash Memory 

For correct programming, a communication sequence to the Flash devices must be used which is defined by the manufacturer of the Flash device. This communication sequence has to be performed on every byte path. Besides the communication sequence, a programming voltage Vpp of 12V must be applied to the Flash device. The Vpp is generated by the CPU-30SEN-R and is controlled by CIO #1 PB5 (Port B, Bit 5).

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