SST 5201-DFNT-DNPSNET Communication module

Boot Flash Memory Device Types and Programming The Boot Flash Memory area is located in two 32-pin PLCC sockets. Both sockets use 12V programmable Flash devices of type 28F010 (128KB) or 28F020 (256KB). Alternatively, EPROM devices (e.g. OTP) up to 256 KB may be mounted. Note: Special assembly Options of the CPU-30SEN-R board allow EPROM devices (e.g. OTP) up to 1MB in one socket and 512 KB (5V Flash devices) in both sockets.

The programming of Boot Flash Memory devices is supported for devices assembled in both sockets. For correct programming, a communication sequence to the Boot Flash Memory devices must be used which is defined by the manufacturer of the device. The programming to the Boot Flash Memory devices is dependent on switch SW6-1, which controls hardware write protection

Address Map with SW9-1 in OFF position 

The table below outlines the address map of the boot flash devices located at socket #1 (J12) and socket #2 (J13) with SW9-1 in the OFF position (default setting). The default boot flash socket #1 is disabled when SW9- 1 is in the ON position.Address map of the Boot Flash socket #1 (J12) and socket #2 (J13) with SW9-1 in the on position. This is not the default configuration.Besides the 32-bit wide System Flash Memory and the two 8-bit wide Boot Flash Memories the CPU board holds also an 128KBytes 8-bit wide User Flash Memory device which allows permanent data storage without the need of backup power.

Memory Organization of the User Flash Memory 

The User Flash Memory is an 8-bit device connected to the I/O bus of the FGA-002, along with the other I/O devices (SCC, RTC, CIO #1, CIO #2, etc.). Data can be read from any address; odd, even or unaligned in byte, word, or long word format. Data can be written to any address in byte format, provided the proper software protocol is followed and the User Flash Memory is not write protected.

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