SST 5201-MNET-DNPSNET Communication module

For correct programming, a communication sequence to the User Flash Memory devices must be used which is defined by the manufacturer of the device. The programming to the User Flash Memory device is dependent on switch SW6-2, which realizes a Hardware-Write protection.Besides the communication sequence, a programming voltage Vpp of 12V must be applied to the Flash device. The Vpp is generated by the CPU-30SEN-R and is controlled by CIO #1 PB5 (Port B, Bit 5).

The start address of the User Flash Memory is mapped via the FGA-002 Gate Array and a programmable Logic device and cannot be changed. The size of this memory area depends on the memory capacity of the devices used. The following table lists the address map for the usable device types.

Memory Organization SRAM 

The CPU board contains a byte-wide local SRAM memory. This is connected to the local 8-bit data bus of the FGA-002 Gate Array. Byte, Word and Longword Read and Writes to any address are possible by the 68030 microprocessor. The FGA-002 Gate Array executes the necessary Byte access to the SRAM on its 8-bit local I/O bus in order to deliver/write the data on CPU Word and Longword accesses.

Devices Used for SRAM Area 

The default SRAM capacity is 128 KByte. As assembly option an 32KByte SRAM device may be used. As the SRAM device is surface mounted, this assembly option is a factory option and can not be done by the user of the CPU-30SEN-R The following low power device types (marked with -L or -LL) are supported.The setup parameters of FGA-002 are located at the beginning of the local SRAM address space (battery backup enabled). Additionally during booting FGA-Boot utilizes the first 8KBytes as local Stack. Therefore the address range FFC0.000016- FFC0.200016 is reserved and no user data should be placed there for permanent storage via battery backup.

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