The SRAM and RTC are powered by backup power circuitry. This circuitry maintains power supply for them to guarantee continuous operation. Under normal operation the backup power circuitry connects the +5V power supply to the SRAM and RTC. When the main +5V supply fails, backup power may be supplied from one of two alternate sources. There are two sources for backup power. One from the APNbus +5VSTDBY line (not available on CPU-30SEN-R-501) and the other one from a CR2032-type lithium battery installed in the battery socket at location BAT 1. As factory option this socket may be removed. Instead, a fixed socketless battery may be assembled for a rugged environment.
Address Map of the Local SRAM
The start address of the local SRAM is mapped via the FGA-002 Gate Array and a programmable Logic device and fixed to FFC0.000016 and cannot be changed. The size of this memory area is 512 KBytes. To minimize hardware overhead and keep costs low only the higher address lines are decoded. Therefore the default 128 KBytes of local SRAM are found four times mirrored in 128 kbytes steps in this 512 KByte area.
The switchover from normal +5V to Backup power is fully automatic; whichever voltage is higher will be available to the RTC and SRAM. Should the +5V and/or +5VSTDBY supplies drop below approximately +3.3 volts, the on-board battery will be used.
The Real-Time Clock (RTC) 72423
There is an RTC 72423 installed on the CPU board, containing its own crystal to maintain accurate time and date. A battery is provided on the CPU board to allow the RTC to run even under power-down conditions The RTC 72423 has a 4-bit data bus. It must be accessed in byte mode and the upper four bits (4..7) are "don’t care" during read and write accesses. The base address of the RTC is FF80.300016. The following table shows the register layout of the RTC 72423.
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