ALSTOM V4555724-0100 Switch input card

RS-232 Interface for SCC Serial I/O Ports #1 and #2 On the CPU-30SEN-R both serial I/O ports are routed to the front panel. Port #1 is available on a standard female 9-pin D-Sub front panel connector. Port #2 instead is available on a special 12-pin front panel header. -R-501 On CPU-30SEN-R-501 both ports are available on standard female 9-pin D-Sub connectors. Both ports support RS-232. The RS-232 interfaces are realized using 5Vonly RS-232 drivers (internal charge pump circuitry). In this way a single +5V supply voltage is sufficient to power the CPU-30SEN-R CPU-board.

The following SYS68K/CPU-30SEN-R parameters can be read or written.

 – timers • reading whether an interrupt request has been generated by one of the timers 2 or 3 from CIO #1 (see table 50 “CIO #1 Port C data register” on page 96 (timer 2) and see table 49 “CIO #1 Port B data register” on page 94 (timer 3)). - DRAM 

• reading the DRAM capacity (see table 54 “CIO #2 Port C data register” on page 99). – ID-ROM 

• controlling and reading the status of ID-ROM signals (see table 49 “CIO #1 Port B data register” on page 94). – MODE x 

• reading the setting of the 2 front panel rotary switches (see table 48 “CIO #1 Port A data register (including MODE x status register)” on page 94).

• A24-to-A32 address translation

 (see table 52 “CIO #2 Port A data register” on page 98), on APNbus-A24 Slave accesses to CPU30SEN-R. (As APNbus supports only A24 accesses, on slave accesses to the CPU-30SEN-R, the 24-bit APNbus address gets expanded to a 32-bit address for the FGA-002. FGA-002 then translates this 32-bit address to a local 32-bit CPU-30SEN-R onboard address.

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