MOOG D136-002-002 Servo drive

T3IRQ controls the interrupt request output for timer 3 of CIO #1. The 16-bit timer can generate interrupt requests at a software programmable level (see FGA-002 User’s Manual). The corresponding interrupt request line is connected to the local IRQ #2 of the FGA-002. Additionally, the timer 3 of CIO #1 can be programmed to generate an interrupt on the interrupt request line which is connected to the local IRQ #6 of the FGA002. For information on the interpretation of the bit value of T3IRQ, see the CIO Z8536 data sheet and the FGA-002 User’s Manual..

All CIO-Pins which are marked as inputs are not allowed to be programmed as outputs. FGA-BOOT Software ensures the correct initialization of the CIO devices. Therefore user-SW shouldn’t reprogram the data-direction registers of the CIO devices. An exception is port B, which is programmed as output by default. It must be configured as input to be able to read the board ID.

These CIO outputs are connected to the corresponding 

FGA-002 VMEbus address inputs. As the APNbus supports only A24 accesses, on slave accesses from an APNbus master to the CPU-30SEN-R, the 24-bit APNbus address gets expanded to a 32-bit address for the FGA-002. FGA-002 then translates this 32-bit address to a local 32-bit CPU-30SEN-R onboard address. As the A24-APNbus can address only 16 MByte of address space it is necessary to change this 8-bit address in CIO #2 to access the whole 32 MBytes of onboard DRAM memory (see FGA-002 User’s Manual, which describes in detail the VMEbus (APNbus) memory translation to onboard local addresses).

When reading these bits directly after power-up or reset

 these bits indicate the CPU board identification number which is assigned to every type of CPU board. The CPU identification number does not identify the factory options which might be available for memory capacity or installed modules. In case of the CPU-30SEN-R boards

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