DEIF PPM-3 Ship control card

DMA transfer from Local I/O Interface to FLXibus During a DMA transfer from the SCSI controller MB87033/34 to the FLXibus (CPUbus), the DMA Controller first transfers data from the I/O device into the FIFO of the used DMA channel. As soon as two FIFO lines (8 bytes) are occupied, the DMA Controller will request the FLXibus (CPUbus). When the DMA Controller has bus mastership on the FLXibus, it transfers the FIFO contents into the memory on the FLXibus.

DMA transfer from FLXibus (CPUbus) to Local I/O Interface

 Before the DMA Controller can start a DMA transfer from the FLXibus to the SCSI-controller MB87033/34, it must request bus mastership on the FLXibus (CPUbus). When the DMA Controller has bus mastership it will transfer data from the FLXibus into the FIFO of the used DMA channel. The DMA Controller then transfers the FIFO contents to the I/O device. As soon as two FIFO lines (8 bytes) are available the DMA Controller requests the FLXibus again. This technique permits the CPU to perform in a real time capacity.

The DMA Interface of the MB87033/34

is directly connected to the 8-bit Local I/O Interface of the FC68165 I/O Controller. The DMA mode of the MB87033/34 is fully supported by the FC68165 I/O Controller. In the DMA-mode the MB87033/34 is accessed by the FC68165 with a DMA request/acknowledge handshake protocol. The DMA request signal of the MB87033/34 is directly connected to the DMA channel #1 (DMAREQ1) of the FC68165. The chipselect signal #7 (CSDEV7) of the FC68165 serves as the DMA acknowledge signal for the MB87033/34. Therefore the "local port" in the "DMA Status Control Register #1" (DMACTRL[1]) of the FC68165 must be set to 7. The FC68165 I/O Controller generates parity to the MB87033/34 in a DMA write access. For detailed information about the DMA Controller of the FC68165 I/O Controller, please refer to the I/O Controller (FC68165) User’s Manual.

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