The FC68165 External Interrupts The table below shows the connection between local devices and the local interrupt request of the FC68165 EAGLE controller. For a complete description of the internal FC68165 interrupt sources (DMA, Timer) and his interrupt handling, please refer to the FC68165 User’s Manual.
The table below shows the connection between local devices and the local interrupt request of the FGA-002. For a complete description of the internal FGA-002 interrupt sources and interrupt handling, please refer to the FGA-002 User’s Manual.
The APNbus Interface
The CPU board contains an APNbus interface. The APNbus interface is realized with the FORCE gate array FGA-002 (VMEbus interface controller) and some glue logic implemented in an APN-LCA, which is a Xilinx FPGA-device (SRAM-based field programmable gate array). The APNbus interface is compatible with the APNbus Specification 1/155 19 - APN 167 01 Uen. The APNbus interface supports a 24-bit address interface (A24) and 8 and 16-bit aligned and unaligned data transfers (D16, D8). Read-Modify-Write cycles on the APNbus are handled as described in the APNbus Specification 1/155 19 - APN 167 01 Uen. The BUSY signal is held low during this cycle while the data strobe signals are driven low twice, once for the read cycle and once for the write cycle, and high between the both of them.
Five APN interrupt requests are connected to the FGA-002’s
VME interrupt request inputs. Every APN interrupt request input can interrupt the local CPU on a software programmable level. A four-level APNbus arbiter together with several bus release functions are implemented with all CPU/System Controller functions such as a BRES driver and receiver and GRI-OUT driver. The following chapters describe the functions of the interface parts in detail. Please see the installation section of this manual for the pinout of the APNbus interface on the backplane connectors for CPU-30SEN-R (VG96 backplane connectors) and CPU-30SEN-R-501 (metric 4-row backplane connectors).
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