ABB HIEE300024R4 UAA326A04 Processing module

Data Transfer Size of the APNbus Interface The APNbus interface contains memory areas where the data transfer size is either 16 bits or 32 bits. The hardware on the CPU board adjusts the transfer size automatically, so that no additional software overhead is necessary. For example, if the local 68030 processor requests a 32-bit read cycle from a 16-bit APN memory board, the CPU board will automatically perform two consecutive 16-bit read cycles.

The APNbus data bus interface to the shared DRAM is 16 bits wide. It supports 16-bit and 8-bit as well as unaligned (UAT) and read-modifywrite (RMW) transfers.

The Access Address 

The onboard shared DRAM of the CPU board is also accessible from the APNbus side. Both the beginning and end addresses are programmable in 4 KByte increments inside the FGA-002. The complete address decoding for the shared DRAM logic is performed inside the FGA-002 Gate Array. For details on the programming of the access address, please refer to the BOOT Software description in the FGA-002 User’s Manual.

The FGA-002 handles all APNbus address 

decoding to the Shared DRAM. The FGA-002 is designed with a 32-bit address bus. It will attempt to decode all 32 bits of address information for all slave access cycles. Because the APN bus specification defines only a 24-bit address bus, onboard hardware must supply the additional 8 address bits. This is handled by the CIO #2 Port A. All 8 bits of Port A are compared against the upper 8 address bits programmed into the FGA-002. The remaining 24 bit are supplied by the current APNbus master. The following table shows which CIO #2 bit corresponds to which address line.

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