The most-significant 4 bits (A31-A28) of the slave address decoding range are programmed at location $FFD00200 in FGA-002 (VMEPAGE Register). The lower 4 bits of this register must match the upper 4 bits of CIO #2 Port A (A[31..28]). The next most-significant 8 bits (A27-A20) of the slave address decoding range are programmed at FGA-002 location $FFD002D0 (BOTTOMPAGEU Register). The upper 4 bits of this register must match the lower 4 bits of CIO #2 Port A (A[27..24]). The APN slave address must also be programmed at FGA002 address $FFD002D8 (TOPPAGEU Register). Again, the upper 4 bits of this register must match the lower 4 bits of CIO #2 Port A.
The lower 4 bits of both the BOTTUMPAGEU Register and the TOPPAGEU Register may be programmed at the user’s discretion. Also, the BOTTOMPAGEL Register and the TOPPAGEL Register are entirely at the user’s discretion. This allows the user to program any 12-bit pattern into the upper and lower slave decoding address ranges, offering over one million possible combinations. Refer to the software description in the FGA-002 User’s Manual for further information
The APNbus Interrupt Handler
Five of the seven APNbus interrupt request (RQI) signals are connected to the interrupt handling logic on the FGA-002 Gate Array. Each of the APNbus RQI signals can be separately enabled or disabled. The FGA002 Gate Array allows high end multiprocessor environment board usage with distributed interrupt handling.
The FGA-002 Gate Array acts
as the interrupt handler in accordance with the APNbus Standard. Therefore the CPU-30SEN-R is the first board in the APNbus Interrupt Acknowledge daisy-chain GRI-IN/GRI-OUT (CPU-30SEN-R drives GRI-OUT, which is backplane-connected to GRIIN of the APNbus board in the following APNbus slot position). Besides the GRI-IN/GRI-OUT daisy-chain, a bused APNbus signal IACK informs all boards on the APNbus of an interrupt-acknowledge cycle in progress. This fast IACK-signal is used for cycle decoding information and fast disconnection of the IACK-daisy chain.
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