The CPU-30SEN-R senses the priorized APNbus bus mastership request lines RQB1, RQB2, RQB3 and drives the three APNbus grant bus signals GRB1O, GRB2O, GRB3O. All other boards plugged into the APNbus rack drive the open collector lines RQB1, RQB2, RQB3 and sense the daisy chained bus grant acknowledge lines GRB1IN. GRB2IN, GRB3IN and drive their GRB1O, GRB2O, GRB3O outputs to close the daisy chain. The CPU-30SEN-R onboard APNbus arbiter arbitrates not only the three APNbus mastership request levels (RQB1,RQB2,RQB3), but also the CPU’s (MC68030) request to APNbus mastership (local CPU-30SEN-R access to FC00.000016-FCFF.FFFF16 ). The arbiter provides a 4-level arbiter function implemented in the APN-LCA device. For correct operation the internal arbiter of the FGA-002 must remain disabled. On CPU accesses to APNbus the FGA-002 requests the APNbus via a local RQB0 signal from the APN-LCA’s 4-level-arbiter. In this way CPU request level to APNbus mastership may be switched on two different priority levels respectively to the fixed APNbus priority sequence RQB3-RQB2-RQB1 (highest to lowest).
The Onboard Four-Level APNbus Arbiter
The CPU board contains a four-level APNbus arbiter which is always enabled. The four-level arbiter is implemented in a programmable gate array (Xilinx LCA). FGA-002’s internal arbiter must remain disabled, because this external APNbus arbiter inside the APN-LCA of the CPU30SEN-R also handles CPU requests for APNbus master accesses. All three APN bus request signals (RQB1, RQB2, RQB3) are monitored by the CPU board, along with the CPU board's own bus request (RQB0). The onboard APNbus arbiter can work in one of two modes. The CPU board can be the lowest priority in the arbitration system, or it can be the next-to-highest priority. The arbiter mode is selected by switch SW5-3 as described below.
The APNbus Release Functions
The CPU board contains several different software-selectable APNbus release functions to relinquish APNbus mastership. Easy handling and usage of the bus release functions is provided through the FGA-002 Gate Array. Read-Modify-Write (RMW) Cycles will always be completed before the bus is released.
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