KONGSBERG RAIC400 control card

VMEPROM allows the user to change the release function through the ARB command. Please refer to the VMEPROM section of this manual for details. The modes are defined in the following sections. Note that all of the following bus release options only apply to APN cycles initiated by the local 68030 microprocessor. Cycles initiated by the onboard DMA controller are not effected. Release Every Cycle (REC) The REC mode causes a release of mastership after every transfer cycle has been completed. A normal read or write cycle is terminated after the data strobes are driven high (inactive state). A Read-Modify-Write (RMW) cycle is terminated after the second (write) cycle is completed by the CPU, through deactivation of the data strobes.

When the REC mode is enabled

 all other bus release functions have no impact ("don’t care"). The REC mode is only for 68030 cycles to the APNbus, and not for cycles from the DMA controller. The programming of the REC mode is described in the FGA-002 Gate Array Manual. Release on Request (ROR) The ROR mode is defined as a release of bus mastership if another APNbus requester has requested APN bus mastership and the CPU board is the current APN bus master. The DMA controller in FGA-002 can also be the bus requestor and cause such a bus release. The ROR mode is only for 68030 cycles to the APNbus, and not for cycles from the DMA controller.

The ROR mode cannot be disabled

 but the user may select how long the CPU board stays APNbus master in spite of a pending bus request. There are 8 possible choices for this time period. The programming of the ROR mode is described in the FGA-002 Gate Array Manual. Note: The CPU board does not distinguish between the levels of the other APN bus requests. After the ROR timeout expires, any APN bus request on any level will cause the CPU board to release its APN bus mastership.

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