Release on Bus Release (RBCLR) The RBCLR function causes an immediate bus release if the APN arbiter asserts the BREL signal. This function then overrides the ROR mode timing limitations. The RBCLR mode only affects 68030 cycles to the APNbus and not cycles from the DMA controller. The programming of the RBCLR mode is described in the FGA-002 Gate Array User’s Manual.If the board is programmed by the Gate Array to be the ACFAIL HANDLER in the APNbus system, and if the VAL (voltage alarm) signal of the APNbus is asserted, the CPU board will not release the APNbus if it is already the APNbus master. That is, REC, ROR, RAT, and RBCLR do not operate in this case. If the board is not ACFAIL HANDLER and the VAL signal is asserted, the board will release the APNbus immediately.
Release After Timeout (RAT)
After every APN access a 100 microsecond RAT timer is started. After this time elapses, the CPU board will release APNbus mastership unless the local microprocessor makes another APN access within the 100 µs time period. After each new access to APN, this 100 µs time period must elapse again before the bus is released. The RAT timer does not begin until the ROR timer has already expired, so the total time may be longer than 100 µs.
This function cannot be disabled.
The RAT mode only affects 68030 cycles to the APNbus and not cycles from the DMA controller. Note that the RAT timer will cause the CPU board to hold APN bus mastership for at least 100 µs whether it uses the APNbus or not. This is often called "bus parking." The CPU board will drive BUSY and MSEL active during this period. The CPU board, will, however, release the APN bus immediately if it receives the BREL signal (and RBREL is enabled), or if it receives another APN bus request (and the ROR timer has expired), or if it receives the VAL signal (and ACFAIL HANDLER is not enabled), or after every APN cycle (and REC mode is enabled).
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