KONGSBERG RDIOR400 ship controller

Release When Done (RWD) The DMA Controller in the FGA-002 Gate Array can also be APNbus master. It always operates in transfer packets (maximum 32 transfers). The bus is always released after completion of such a transfer packet. The other bus release functions are for 68030 mastership to the APNbus. The table on the next page outlines the bus release functions

Front Panel 12-Pin Header Reset Connector On the CPU-30SEN-R there is a front panel 12-pin header connector which provides the signals necessary for remote reset and abort control. -R-501 This 12-pin front panel header is not available on the CPU-30SEN-R-501 variant of this CPU board.

APNbus Timeout Timer

 The CPU-30SEN-R has implemented a Bus Timeout Timer to terminate APNbus transfers which are not terminated regularly. The CPU-30SENR always supervises the APNbus signals UDS and LDS, which indicate an APNbus cycle in progress. If the timeout period of 10 µsec elapses before a valid APNbus cycle termination occurs (EACK, DTACK) the APNbus Timeout timer asserts itself the APNbus error acknowledgement signal EACK, and so the APNbus cycle is terminated

APNbus Exception Signal APN-VAL 

The APNbus specification defines the signal VAL (voltage alarm) for signaling failure of main power. The CPU-30SEN-R board always monitors the VAL signal from the APNbus. The FGA-002 may be programmed to generate interrupts on the assertion of VAL. The FGA-002 may also be programmed to either release APNbus mastership, or to maintain APNbus mastership on the assertion of VAL. The VAL line is ignored by VMEPROM. For detailed information please refer to the FGA-002 User’s Manual. The CPU-30SEN-R cannot drive the VAL signal to the APNbus.

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