There is an APNbus Specification 1/155 19 - APN 167 01 Uen compatible BRES driver installed on the CPU board. The RESET generator circuitry operates when the power supply reaches at least the 3 volt level. The RESET signal can be asserted (low) on any one of the following conditions:
• Front Panel RESET switch toggled -R-501
• Remote RESET switch toggled (not available on -501-variant)
• Voltage Sensor (TL7705) detects VCC below limit (4.85 V)
• Execution of the RESET instruction by the CPU MC68030 on the CPU-30SEN-R board
• Programmable RESET watchdog timer expires (must be enabled by SW5-2)
• APNbus signal BST
• Access to FGA-002 Reset Register
Front Panel Reset Switch
The upper switch on the front panel of the CPU board is the RESET switch. Toggling it provides a reset of all on-board devices and the APNbus backplane by assertion of APNbus signal BRES. When the RUN LED is red, the processor is in the HALT state. For example, this state will be entered if a double bus fault occurs. A reset of the board must be performed by toggling the RESET switch or by asserting the BRES backplane signal. The RUN/HALT LED is also red while the RESET generator drives the reset. After reset, the RUN/HALT LED will change to green.
The RESET Instruction
The RESET instruction of the microprocessor is designed to reset peripherals under program control, without resetting the processor itself. This instruction is fully supported by the CPU board. The RESET instruction resets all peripherals on the board driving reset to low. At this point the processor on the CPU itself will not be reset. Therefore, program execution will go on with the next operation code. If another board asserts BRES before this instruction triggered reset has ended, then the processor will still not be reset. If the option is enabled inside FGA-002, the CPU board will also drive the APN signal BRES during a processor reset instruction. The VME interface inside of the FGA-002 needs 250 ms to reset. Do not access the FGA-002 during this time.
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