A Watchdog circuit function may be enabled with help of CIO #1 Timer2 and switch SW5-2. By default SW5-2 is in OFF position, so that CIO #1’s Timer 2 output is routed to FGA-002 LIRQ3 input to generate a Interrupt to the CPU. By turning the SW5-2 on and programming the CIO #1 Timer2 a Software-WDOG function may be realized. In this case if the programmed Timer 2 WDOG timeout period elapses without retriggering of Timer 2, the Timer 2 output directly drives the board’s reset signal. RESET will stay asserted for at least 200 milliseconds after WDOG reset assertion.
Voltage Sensor TL7705 (Reset Generator)
The voltage sensor serves as a reset generator. Power up reset is provided by this sensor, as soon as the supply voltage VCC has reached approximately 3 volts. The local reset signal will be asserted when the board supply voltage VCC subsequently falls below 4.85 Volts. RESET will be asserted if VCC is less than 4.85 volts on the board, if the SW5-1 is in OFF position, which is default. If SW5-1 is turnend ON, RESET will be asserted if VCC is less than 4.7 Volts. In either case, RESET will stay asserted for at least 200 milliseconds after the supply voltage has passed the threshold.
This CPU board operates under the control of VMEPROM
a ROM resident real-time multiuser multitasking monitor program. VMEPROM provides the user with a debugging tool for single and multitasking real-time applications. Common and hardware specific details All common commands and system calls are described in the VMEPROM Version 2/32 User’s Manual. This section describes those parts of VMEPROM which pertain to the hardware of this CPU board. Features of VMEPROM • Line assembler/disassembler • Numerous commands for program debugging, including breakpoints, tracing, processor register display and modify
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