ABB BC810K02 3BSE031155R1 processor module

Level processing within one of the two time slices is interrupted by alarm level 11 as discussed under item 1. The time for processing the levels within the time slices is reduced by the higher priority levels 0 to 8 which, like levels 9 and 10, can only be called by the system. The maximum time available for levels 0 to 10 is 100 ms per second. – Residual time If any time is remaining within the 1–second cycle, which is subdivided in an 3:1 ratio, after the program execution of one time slice has been completed, this is made available for the other time slice. Time slice 1.1 has priority over time slice 1.2. – Transition from time slice procedure to priority–controlled processing

Instead of the time slice procedure

which is suspended for the current 1–second cycle after the programs of the second time slice have also been executed completely, priority– controlled processing of levels 0 to 15 (0 has highest, 15 lowest priority) is assumed. From this point in time, processing of level 15 (ZYK 5, background level) is possible, provided that execution of all levels with higher priority has been completed. Approximate values for the time division – related to one second – are: The system needs 100 ms per second for processing levels 0 to 1. 700 ms per second are allocated to levels 11 (not processed in time slice procedure), 12 (125–ms cycle) and 13 (1–second cycle). 200 ms per second are given to levels 14 (operation, display/log output) and 15 (background level)

Frequent interrupt processing

high I/O bus requests (N8) and residual time values of the two time slices may cause relocation of this time distribution. Example 1: Level 11 is not activated (no alarm processing required); level 12 requires 30 ms per cycle (i.e. 30 x 8 = 240 ms per second); level 13 needs 300 ms and level 14 210 ms. With a system load of approx. 100 ms, approximately 150 ms remain for the background level. Example 2: If the levels 11, 13 and 14 together require only 100 ms, 900–100 = 800 ms per second are left for level 12. Without any cycle 3 (level 13) or operator input processing, 800:8 = 125 ms per 125–ms cycle are thus available for the user. A cycle overflow will occur in example 2 if additional requirements caused by alarm processing or system operator input arise.

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