GE IS200EHPAG1D Logic sequence module

The RDNA driver program runs on the host. The DPP array is the heart of the RDNA processor. The array is organized as a set of workgroup processor pipelines, each independent from the others, that operate in parallel on streams of floating-point or integer data. The workgroup processor pipelines can process data or, through the memory controller, transfer data to, or from, memory. Computation in a workgroup processor pipeline can be made conditional. Outputs written to memory can also be made conditional. When it receives a request, the workgroup processor pipeline loads instructions and data from memory, begins execution, and continues until the end of the kernel. As kernels are running, the RDNA hardware automatically fetches instructions from memory into on-chip caches; RDNA software plays no role in this. RDNA kernels can load data from off-chip memory into on-chip general-purpose registers (GPRs) and caches.

The AMD RDNA devices 

can detect floating point exceptions and can generate interrupts. In particular, they detect IEEE floating-point exceptions in hardware; these can be recorded for post-execution analysis. The software interrupts shown in the previous figure from the command processor to the host represent hardware-generated interrupts for signaling commandcompletion and related management functions. The RDNA processor hides memory latency by keeping track of potentially hundreds of workitems in different stages of execution, and by overlapping compute operations with memoryaccess operations.

Program Organization RDNA 

kernels are programs executed by the RDNA processor. Conceptually, the kernel is executed independently on every work-item, but in reality the RDNA processor groups 32 or 64 work-items into a wavefront, which executes the kernel on all 32 or 64 work-items in one pass. The RDNA processor consists of: • A scalar ALU, which operates on one value per wavefront (common to all work items). • A vector ALU, which operates on unique values per work-item. • Local data storage, which allows work-items within a workgroup to communicate and share data. • Scalar memory, which can transfer data between SGPRs and memory through a cache. • Vector memory, which can transfer data between VGPRs and memory, including sampling texture maps.

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