GE IS200STAIH1ABB DC output card

◦ If the LDS-ADDRESS is out-of-range (addr < 0 or > (MIN(lds_size, m0)): ▪ Writes out-of-range are discarded; it is undefined if SIZE is not a multiple of writedata-size. ▪ Reads return the value zero. 

 If any source-VGPR is out-of-range, the VGPR0 value is used. 

◦ If the dest-VGPR is out of range, nullify the instruction (issue with exec=0) • Memory, LDS, and GDS: Reads and atomics with returns. 

◦ If any source VGPR or SGPR is out-of-range, the data value is undefined. 

◦ If any destination VGPR is out-of-range, the operation is nullified by issuing the instruction as if the EXEC mask were cleared to 0. ▪ This out-of-range check must check all VGPRs that can be returned (for example: VDST to VDST+3 for a BUFFER_LOAD_DWORDx4).

SGPR Allocation and storage 

Every wavefront is allocated a fixed number of SGPRs: • 106 normal SGPRs • VCCh and VCCl (stored in SGPRs 106 and 107) • 16 Trap-temporary SGPRs, meant for use by the trap handler ▪ This check must also include the extra PRT (partially resident texture) VGPR and nullify the fetch if this VGPR is out-of-range, no matter whether the texture system actually returns this value or not. ▪ Atomic operations with out-of-range destination VGPRs are nullified: issued, but with exec mask of zero. Instructions with multiple destinations (for example: V_ADDC): if any destination is out-of-range, no results are written.

SGPR Alignment 

Even-aligned SGPRs are required in the following cases. • When 64-bit data is used. This is required for moves to/from 64-bit registers, including the PC. • When scalar memory reads that the address-base comes from an SGPR-pair (either in SGPR). Quad-alignment is required for the data-GPR when a scalar memory read returns four or more Dwords. When a 64-bit quantity is stored in SGPRs, the LSBs are in SGPR[n], and the MSBs are in SGPR[n+1].

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