ABB 57160001-UH DSTD 150A Key module

Flat instructions can complete out of order with each other. If one flat instruction finds all of its data in Texture cache, and the next finds all of its data in LDS, the second instruction might complete first. If the two fetches return data to the same VGPR, the result are unknown.Since the data for a FLAT load can come from either LDS or the texture cache, and because these units have different latencies, there is a potential race condition with respect to the VM_CNT/VS_CNT and LGKM_CNT counters. Because of this, the only sensible S_WAITCNT value to use after FLAT instructions is zero.

Addressing 

FLAT instructions support both 64- and 32-bit addressing. The address size is set using a mode register (PTR32), and a local copy of the value is stored per wave. The addresses for the aperture check differ in 32- and 64-bit mode; however, this is not covered here. 64-bit addresses are stored with the LSBs in the VGPR at ADDR, and the MSBs in the VGPR at ADDR+1. For scratch space, the texture unit takes the address from the VGPR and does the following

Legal Addressing Combinations

 Not every combination of addressing modes is legal for each type of instruction. The legal combinations are: • FLAT a. VGPR (32 or 64 bit) supplies the complete address. SADDR must be NULL. • Global a. VGPR (32 or 64 bit) supplies the address. Indicated by: SADDR == NULL. b. SGPR (64 bit) supplies an address, and a VGPR (32 bit) supplies an offset • SCRATCH a. VGPR (32 bit) supplies an offset. Indicated by SADDR==NULL. b. SGPR (32 bit) supplies an offset. Indicated by SADDR!=NULL. Every mode above can also add the "instruction immediate offset" to the address.

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