ABB 57520001-BZ DSCS 116 Voltage input card

Compare instructions perform the same compare operation on each lane (workItem or thread) using that lane’s private data, and producing a 1 bit result per lane into VCC or EXEC. Instructions in this format may use a 32-bit literal constant or SDWA which occurs immediately after the instruction. Most compare instructions fall into one of two categories: • Those which can use one of 16 compare operations (floating point types). "{COMPF}" • Those which can use one of 8 compare operations (integer types). "{COMPI}" The opcode number is such that for these the opcode number can be calculated from a base opcode number for the data type, plus an offset for the specific compare operation.

VOPC using VOP3A encoding 

Instructions in this format may also be encoded as VOP3A. VOP3A allows access to the extra control bits (e.g. ABS, OMOD) at the expense of a larger instruction word. The VOP3A opcode is: VOP2 opcode + 0x000. When the CLAMP microcode bit is set to 1, these compare instructions signal an exception when either of the inputs is NaN. When CLAMP is set to zero, NaN does not signal an exception. The second eight VOPC instructions have {OP8} embedded in them. This refers to each of the compare operations listed below.Flat instructions look at the per-workitem address and determine for each work item if the target memory address is in global, private or scratch memory.

EXPORT Instructions

 Transfer vertex position, vertex parameter, pixel color, or pixel depth information to the output buffer. Every pixel shader must do at least one export to a color, depth or NULL target with the VM bit set to 1. This communicates the pixel-valid mask to the color and depth buffers. Every pixel does only one of the above export types with the DONE bit set to 1. Vertex shaders must do one or more position exports, and at least one parameter export. The final position export must have the DONE bit set to 1.

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