RELIANCE 0-574301-C Voltage monitoring input card

The MVME162 provides +5 Vdc power to the remote LED/switch connector (J4) through a 1A fuse (F1) located near J4. Connector J4 is the interface for a remote control and indicator panel. If none of the LEDs light and the ABORT and RESET switches do not operate, check fuse F1. The MVME162 provides +12 Vdc power to the Ethernet transceiver interface through a 1A fuse (F2) located near diode CR1. The FUSE LED lights to indicate that +12 Vdc is available. When the MVME712M module is used, the yellow DS1 LED on the MVME712M illuminates when LAN power is available, which indicates that the fuse is good. If the Ethernet transceiver fails to operate, check fuse F2. The MVME162 provides SCSI terminator power through a 1A fuse (F1) located on the P2 Adapter Board or LCP2 Adapter Board. If the fuse is blown, the SCSI device(s) may function erratically or not at all.

This chapter provides information 

necessary to use the MVME162 in a system configuration. This includes a description of the switches and LEDs, memory maps, and software initialization of the module. Switches and LEDs The MVME162 front panel has ABORT and RESET switches and eight LED (light-emitting diode) indicators (FAIL, STAT, RUN, SCON, LAN, FUSE, SCSI, VME). ABORT Switch (S1) When enabled by software, the ABORT switch generates an interrupt at a userprogrammable level. It is normally used to abort program execution and return to the 162Bug debugger firmware located in the MVME162 EPROM and Flash memory. The ABORT switch interrupter in the MCchip ASIC is an edge-sensitive interrupter connected to the ABORT switch. This interrupter is filtered to remove switch bounce.

RESET Switch (S2)

 The RESET switch resets all onboard devices; it also drives SYSRESET* if the MVME162 is the system controller. The RESET switch may be disabled by software. The VMEchip2 includes both a global and a local reset driver. When the VMEchip2 operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET*. A SYSRESET* may be generated by the RESET switch, a power-up reset, a watchdog timeout, or by a control bit in the LCSR in the VMEchip2. SYSRESET* remains asserted for at least 200 ms, as required by the VMEbus specification.

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