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RELIANCE 45C613 Channel isolation module

The MVME172LX may be ordered with an MC68060 or MC68LC060 microprocessor. The MC68060 has on-chip instruction and data caches and a floating point processor. (The floating point coprocessor is the major difference between the MC68060 and MC68LC060.) Refer to the M68060 user’s manual for more information.The MVME172LX local bus masters (VMEchip2, MC68060/MC68LC060, 53C710 SCSI controller, and 82596CA Ethernet controller) have programmable control of the snoop/caching mode. The MVME172LX local bus slaves which support MC68060/MC68LC060 bus snooping are defined in the “Local Bus Memory Map” in the MVME172 VME Embedded Controller Programmer’s Reference Guide. The Industry Pack DMA has jumpers to control the state of the snoop control signals.

No-VMEbus-Interface Option

The MVME172LX may be operated as an embedded controller without the VMEbus interface. To support this feature, certain logic in the VMEchip2 has been duplicated in the MC2chip. This logic is inhibited in the MC2chip when the VMEchip2 is present. The enables for these functions are controlled by software and MC2chip hardware initialization. Memory Options The following memory options are available on the different versions of MVME172LX boards.

DRAM Options

The MVME172LX offers the following DRAM options: either 4MB, 8MB, or 16MB shared DRAM with programmable parity on a mezzanine module, or 4MB, 8MB, 16MB, 32MB, and 64MB ECC DRAM on a mezzanine board. The DRAM architecture for non-ECC memory is noninterleaved for 4MB or 8MB and interleaved for 16MB. Parity protection is enabled with interrupts or bus exception when a parity error is detected. DRAM performance is specified in the section on the DRAM Memory Controller in the MC2chip Programming Model in the MVME172 VME Embedded Controller Programmer’s Reference Guide.