RELIANCE 45C341 Digital I/O Template

This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2. 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal. 6. The SRAM has optional battery backup on the MVME177. The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map.

For a complete description of the register bits

 refer to the data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory maps. 2. On the MVME177 this area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and terminates by a TEA signal. 3. Byte reads should be used to read the interrupt vector. These locations do not respond when an interrupt is not pending. If the local bus timer is enabled, the access times out and terminates by a TEA signal. 4. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits.

Software Initialization

 Most functions that have been enabled with switches or jumpers on other modules are enabled by setting control registers on the MVME177. At power up or reset, the EPROMs that contain the 177Bug debugging package set up the default values of many of these registers. Specific programming details may be determined by study of the M68060 Microprocessor User's Manual. You can also check the details of all the MVME177 onboard registers as given in the Single Board Computers Programmer's Reference Guide.

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