The MC68060 microprocessor is the main processor for the MVME177. The superscalar MC68060 processor has: ❏ Two MC68040-compatible CPU integer cores ❏ MC68040-compatible floating point core ❏ Independent 8KB instruction and operand data caches ❏ MC68040-compatible paged memory management unit ❏ A bus controller The processor is in a PGA socket. Its clock speed is 50 MHz (for the -00x models), and 60 MHz (for the -01x models). Note that the local processor bus runs at only half the processor speed. Refer to the MC68060 user's manual for more information.
Flash write protection is programmable
through the VMEchip2 GPIO register. The address map location of Flash is at $000000 through at local reset if the FLASHJP jumper (J8) is in, providing for the all-Flash mode. In the mixed EPROM/Flash mode, half of the Flash is accessable at addresses $200000 through , depending on the condition of the VMEchip2 GPIO2 bit. Because the MVME177 uses 1M x 8-bit Flash memory devices and EPROMs with no download ROM, the software programs the VMEchip2 ROM0 and REV EROM bits properly so that the Flash/EPROM appears at address $0 after powerup. The hardware is implemented so that the EPROM/Flash appears at address $00000000 following a local bus reset.
The EPROMs as shipped are normally
used for the onboard debugger firmware (177Bug), but could be used to download user code to Flash. The EPROMs make up only 1MB of memory, but can share the first 2MB of space with the first 2MB of Flash. The EPROMs occupy only 1MB space in the ROM space in mixed mode and will be repeated in the second 1MB space (which is reserved for future expansion). The EPROMs could coexist with this 2MB of Flash, or could be used to program all 4MB of Flash, then the J8 jumper could be removed to make only Flash available.The MVME177 implements Flash write protection through clearing a control bit (GPIO1) in the GPIO register in the VMEchip2, to enable write by the software after download process/ programming is completed.
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