Pacific Scientific PC832-001-T Digital signal module

Each time the board is powered, the DS1210S checks power sources, allowing software to provide an early warning to avoid data loss: ❏ If the voltage of the backup sources is less than two volts, the second memory access cycle is blocked. ❏ Because the DS1210S may block the second access, the software should do at least two accesses before relying on the data. With the optional battery backup, the MVME187 provides jumpers (see Optional SRAM Backup Power Source Select Header J6 on page 3-11) that allow either power source of the DS1210S to be connected to the VMEbus +5 V STDBY pin or to one cell of the onboard battery. The power leads from the battery are exposed on the solder side of the board, therefore the board should not be placed on a conductive surface or stored in a conductive bag unless the battery is removed.

Lithium batteries incorporate inflammable 

materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents. ❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate. ❏ Do not apply solder directly. ❏ Do not use different models. ❏ Do not charge. ❏ Always check proper polarity.

To remove the battery from the module, carefully pull the battery from the socket. (Data will be lost if a new battery is not installed within 30 seconds.) Before installing a new battery, ensure that the battery pins are clean. Note the battery polarity and press the battery into the socket.

Onboard DRAM 

The MVME187 onboard DRAM is located on a mezzanine board. The mezzanine boards are available in different sizes and with parity protection or ECC protection. Note Parity mezzanines are only supported on 25 MHz main boards.Motorola software does support mixed parity and ECC memory boards on the same main board. The DRAM is four-way interleaved to efficiently support cache burst cycles. Onboard DRAM mezzanines are available in these configurations: ❏ 4, 8, 16, or 32MB with parity protection ❏ 4, 8, 16, 32, 64, or 128 MB with ECC protection

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