RELIANCE 45C380 Bus interface module

Eight software-programmable hardware interrupts are provided by the VMEchip2. These interrupts allow software to create a hardware interrupt. Local Bus Timeout The MVME187 provides a timeout function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by software for 8 µsec, 64 µsec, 256 µsec, or infinite. The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer.

Local Bus Memory Map 

The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes. Normal Address Range Devices The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. ❏ On the MVME187, Transfer Types 0 and 1 define the normal address range.

❏ The cache inhibit function is programmable in the MMUs. ❏ The onboard I/O space must be marked cache inhibit and serialized in its page table.

Memory Maps

 There are two points of view for memory maps: 1. Local bus memory map – the mapping of all resources as viewed by local bus masters 2. VMEbus memory map – the mapping of onboard resources as viewed by VMEbus Masters This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MEMC040 or MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2. 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5. This area is not decoded. If these locations are accessed and the local bus timer is enabled, the cycle times out and is terminated by a TEA signal.

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