RELIANCE 45C951 Bus interface card

Notes 1. For a complete description of the register bits, refer to the Single Board Computers Programmer's Reference Guide or to the data sheet for the specific chip. 

2. Byte reads should be used to read the interrupt vector. These locations do not respond when an interrupt is not pending. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 

3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits. 

4. This area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 

5. This area does return an acknowledge signal. 6. Size is approximate.

VMEbus Memory Map

 This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A. VMEbus Accesses to the Local Bus The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME187 responds to. VMEbus Short I/O Memory Map The VMEchip2 includes a user-programmable map decoder for the GCSR. The GCSR map decoder allows you to program the starting address of the GCSR in the VMEbus short I/O space.

This Chapter Covers

 This chapter provides instructions on: ❏ Unpacking the equipment ❏ Preparing the hardware ❏ Installing the MVME187 RISC Single Board Computer Note that hardware preparation instructions for the MVME712X transition module are provided in separate user’s manuals for each model. Refer to the user’s manual you received with your MVME712X.

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