WOODWARD 5500-510 Servo driver module

Real· Time Clock Registers Address Map The real-time clock registers are byte-wide registers mapped to 32-bit addresses. The data is mapped to the least-significant byte {bits 7 through 0). Byte or halfword accesses are permitted, but (for consistency) not recommended. These registers occupy the last eight locations of the 2048 reserved for the BatteryBacked-up RAM/Real-Time Oock (BBRAMIRTq. Refer to the MK48T02 data sheet listed in the Related Documentation section in Chapter 1 for explanation of the bit assignments of the register functions listed in Table 3-12.

The 68692 DUART registers are byte-wide registers mapped to 32-bit addresses. The data is mapped to the least-significant byte {bits 7 through 0). Byte or halfword accesses are permitted, but (for consistency) not recommended. DUART registers assigned addresses are given in Table 3-13. Refer to register function descriptions and bit assignments in the 68692 data sheet in the Related Documentation section in Chapter 1. The 68692 is a CMOS version of the MC68681

CIO (Counter-Timer) Registers Address Map

 The Z8536 Counter/Timer and Parallel 1/0 Unit (CIO) registers are byte-wide registers mapped to 32-bit addresses. The data is mapped to the least-significant byte (bits 7 through 0). Byte or half-word accesses are permitted, but (for consistency) not recommended. The assigned addresses of the CIO registers are shown in Table 3-14. The Z8536 is a non-multiplexed bus version of the Z8036. The register bit assignments are the same, but accessing the registers requires a two-step procedure rather than the simple read/write of the Z8036. For a description of the bit assignments and register functions, refer to the Z8536 data sheet listed in the Related Documentation section in Chapter 1.

Because Z8536 register access requires two bus cycles

 care must be exercised in the MVME188A multi-C~U environment. If two or more CPUs attempt simultaneous CIO access, the register reads and/or writes will be interleaved. This will most likely produce an invalid access sequence resulting in erroneous data being written to or read from the CIO

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