WOODWARD 5500-563 governor

The MVME188A does not generate a OTACK• to the VMEbus on location monitor accesses. Typically, a BERR• (from the VMEbus time-out timer) is used to end the cycle, unless the bus master generates a DTACK• for location monitor accesses. The MVME188A location monitors respond to 008 (EO) or 016 accesses (i.e., LWORIY must be negated). The GCSR registers respond to 008 (0) or 016 accesses.The VMEbus slave address space is mapped in 4MB pages in a manner similar to M bus address space. Only A32 and A24 spaces are mappable via software; the A16 base address is fixed by DIP switch settings. (Refer to the previous section, and to the Hardware Preparation section in Chapter 2.) The A32 and A24 spaces are individually mappable (in 4MB pages) by the VMEbus SRAM address decoder. The WV AD register is used to load the decoder, and the RV AD register is used to read back the decoder contents. (Refer to Chapter 4 for the description of the VMEbus Slave Address Decoder and all the main logic board (CPU board) registers.)

For VMEbus A32 slave accesses

VMEbus address bits A31 through A22 select a page, and AMS through AM4 determine which one of the decoder maps is used (A32 or A24). If the selected page in the selected maf' is configured to be in VMEbus A32 space, and AM3 = 1, all 32 bits of the VMEbus address are used to address an M bus device. VMEbus A24 slave accesses are handled in a similar manner. VMEbus address bits A31 through A24 supply the top eight bits of the page address, and VMEbus address bits A23 through A22 supply the remaining two. Note that because VMEbus address bits A31 through A24 may or may not be driven during an A24 access, all 256 locations in the SRAM that have the same lower two address bits must be written with the same value. Effectively, the SRAM decoder has only four locations (one for each 4MB page contained within VMEbus A24 space). The decoder map (A24 or A32) is selected in the same manner as above (decoded from AMS through AM4).

If the selected page is configured to be in VMEbus A24 space

 and AM3 = 1, the EXTAD register (top eight bits) and VMEbus address (remaining address bits) form an address used to access an M bus device. As long as the V ADV bit in the CCSR is set, the VMEbus is constantly monitored for cycles in which the address and address modifiers (A24 or A32 only) select a matching mapped page. When this occurs, a request is generated to the M bus arbiter for a VMEbus cycle. Note that VMEbus master space is not accessible from VMEbus slave space; it is possible (but not recommended) to set up the VMEbus and M bus address decoders in this configuration. Any attempt to do this will result in a bus error being returned on the VMEbus cycle.

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