WOODWARD 5501-003 Driver module

Software Initialization Most functions that have been done with switches or jumpers on other modules are done by setting control registers on the MVME188A. At powerup or reset, the EPROMs that contain the 188Bug debugging package set up the default values of many of these registers. Address decoding is done by SRAMs that are also initially set up by the EPROMs. Specific programming details may be determined by study of the MC88100 RISC Microprocessor User's Manual, the MC88200 Cache/Memory Management Unit User's Manual, and the MC88204 64K-Byte Cache/Memory Management Unit (CMMU) data sheet. Then check the details of all the MVME188A on-board registers as given in Chapter 4 of this manual.

Multi-CPU Programming Considerations 

The multiple-CPU architecture of the HYPERmodule requires some special care in the use of some of the MVME188A registers. Good programming practice dictates that only one CPU at a time have control of the control registers. Of particular note are: registers that modify the address map {WMAD, WVAD, CCSR bits MADVNADV); registers that require two cycles to access (00 registers); and VMEbus interrupt request registers (VIRQLV, VIRQV). The GLBRES register should also be used with caution, because its action can be aborted by a local reset from the watchdog timer (perhaps controlled by a different CPU). The CMMU page tables should NEVER be located out on the VMEbus. The CMMU does not support retry protocol on the last cycle of a table-walk operation. If the CMMU page tables map to a VMEbus address and another master tries to access an MVME188A resource in between the last two cycles of a table-walk, a fatal CMMU error will occur.

Local Reset Operation Local reset 

(LRS1) is a subset of system reset (SRS1). Local reset can be generated three ways: expiration of the watchdog timer, pressing the front panel RESET switch (if the SCON switch is off), or by asserting the R&H bit in the GCSR. A local reset removes any pending GLBRES. A GLBRES is made pending by any write to the GLBRES register. It may take up to 32 usec for the resulting system reset to occur. During this time, the assertion of local reset from any of its three sources clears the pending GLBRES (and thus prevents a system reset from being generated). This could be a concern in a multi-CPU or multi-MVME188A system if the watchdog and/or accesses to the GCSR are not carefully controlled. Note that the front-panel RESET pushbutton switch could also prevent a system reset from being generated (if the SCON switch is off) if it was pressed at just the right time.

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