The following sections describe in detail the system controller board registers and their functions, as well as the state of all bits at power-up time (SRST) or after a local reset (LRST). All registers (with the exception of the GCSR) are located on 4-byte boundaries. Accesses to all of these registers should be 32-bit operations. All accesses to the GCSR should be 8-bit or 16-bit operations. Unless otherwise noted in the register bit descriptions, all undefined bits will be read as "1". Undefined bits are ignored on writes. All of the following registers reside on the system controller board; some are contained within LSI parts (such as the 68692 DUART). Registers that are described in an LSI data sheet are not further described here, unless their functions are defined by external hardware (such as which DUART pins connect to RTS, CTS, etc). Please refer to the data sheets of the 68692 DUART, Z8536 CIO, and MK48T02 clock for specific operation of these parts.
68692 DUART Registers
The DUART register bit assignments are described in the 68692 data sheet. How the hardware connection is made to each of the EIA-232-D serial ports on the MVME188A front panel is shown in Table 4-1. This table provides all of the required information to properly initialize and use the two serial ports. Given the clock rate of the DUART {3.6864 MHz), a square wave can be produced with anywhere from 540 nsec to 563 msec period. In lx clock mode, the range is 542 nsec to 35.5 msec in 542 nsec increments. In 16x clock mode, the range is 8.6 µ.sec to 568 msec in 8.6 µ.sec increments. All these times are approximate; actual values can be calculated from the formula in the DUART data sheet.
Z8536 CIO Registers
The CIO register bit assignments are described in the Z8536 data sheet. What hardware connection is made to each of the CIO pins that are used is shown in Table 4-2. This table provides required data to properly initialize and use the three.CIO timers. The clock rate of the 00 is 4 MHz; a square wave can be produced with anywhere from 1 µs to 4295 s (71 min.) period. Using only one timer, the range is 1 µs to 65.5 ms in 1 µs increments. By using two cascaded timers, the range can be increased a factor of 65536. This yields a minimum period of 1 µs, and a maximum period of 4295 s (in 1 µs increments). All these times are approximate; actual values can be calculated from the count values loaded into 00 registers based on a PCLK of 4 MHz (250 ns period).
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