WOODWARD 5501-367 Logic operation module

Several timer I/O pins are brought out to two optional header areas (timer control headers). The pinouts for these headers are described in the Hardware Preparation section in Chapter 2. Normally these two headers do not have pins in production versions; instead, a zero-ohm shunt (R37) is installed to connect the output of timer #2 to the input of timer #3 so the timers can be cascaded. Note that the CIO is given a hardware reset whenever SRST or LRST is asserted.

Set software interrupt request corresponding to this bit. 0 : Do nothing to the software interrupt request corresponding to this bit. NOTE: The state of each SWI bit is reflected in the IST register.

Interrupt Enable and Status Registers

 The Interrupt Status (IST) and Interrupt Enable (IENO through IEN3) registers all have the same bit assignments. These are shown in Table 4-3. The IST register shows the current state of all interrupt requests, independent of any enables. The IENO through IEN3 registers (one for each processor) allow each individual interrupt to be enabled. For each active-high IEN register bit, a logic 1 enables the corresponding interrupt. All IEN bits are cleared to 0 on SRST or LRST. Because the IST register reflects the state of the interrupt requests, IST bits are not directly affected by reset. Interrupt requests may or may not go away with reset; some may have to be cleared by software before use. All reserved interrupt request bits are read as "O" (negated).

SETSWI Register 

The SETSWI register is used by the software to generate an interrupt. It is not really a register itself, but it is used to control the setting of the SWI bits. The state of the SWI bits can be read from the interrupt status (151) register. For every SETSWI bit that is written as a "l", the corresponding SWI bit is set (requesting an interrupt). Every bit that is written as a ''O" does nothing. This makes each SWI bit individually settable by writing a '1" to the corresponding bit in the SETSWI register. Bit assignments are shown in Table 4-4. Because this location is write only, it is unaffected by reset. (However, all SWI bits are cleared by SRST or LRST.)

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