HIMA F1107  Displacement speed module

VMEbus Requester To obtain the VMEbus for both interrupt handling and data transfers, a bus requester is used which is configurable for any level. It supports the RWD, ROR, and FAIR modes for data transfer. 7-Level VMEbus Interrupt Requester An interrupt on any of the seven VMEbus levels can be generated by writing the interrupt vector into the 8-bit VME IRQ vector register (VIRQV) and then writing the interrupt level into the appropriate system control register (VIRQL V). The specified interrupt line is kept asserted until a VMEbus interrupt acknowledge cycle occurs on the requested level; this causes a read of the VIRQV register and a release of the interrupt request. Only one interrupt request may be active at a time.

7-Level VMEbus Interrupt Handler

 The interrupt enable lines can be individually set by software to allow one or more of the seven VMEbus interrupt requests to generate an MVME188A interrupt. Interrupt handler software reads one of the VMEbus IACK cycle registers (VIACKlV through VIACK7V) to initiate a VMEbus IACK cycle. Each VIACK(n)V register is used to acknowledge interrupts on a different VMEbus interrupt level. The IACK cycle is a read of the 8-bit interrupt vector from the interrupt requester by the active processor.

25-Line Orthogonal Multiprocessor Interrupt Controller 

All local interrupts for the HYPERmodule CPUs are controlled by logic on the system controller board. There are no CPU interrupt restrictions. Every processor can receive any interrupt. Any processor can disable any interrupt. Software must use the individual interrupt enable bits to coordinate interrupts. Although the interrupt controller is given no hardware knowledge of CPU level, a group/level organization can be programmed into the interrupt handler. Additional interrupts (SWI7:0) enable one processor to interrupt the other (2-processor model), or one processor to interrupt any of the other three processors (4-processor model).

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