HIMA F1201 Displacement speed clamp

Each processor has one 32-bit register (IEN) of interrupt enables that any of the processors can read or write. A single IST register provides the states of all the individual interrupt request lines. Interrupt handling software is responsible for disabling an interrupt request by changing the state of the individual enabling bit in the appropriate IEN register. Any reset (power-on, system, or local) disables interrupts by clearing all bits of all four IEN registers. Power-on, SRST, and LRST also clears all interrupt requests generated by the MVME188A.The MVME188A system controller board front panel contains three LEDs: FAIL, HALT, and RUN. Refer to Chapter 3 for detailed information on each. Control Switches Two momentary-action switches are provided on the MVME188A system controller board front panel: ABORT and RESET. Refer to Chapter 3 for detailed information on them

Onboard Switches

 The system controller board contains 16 onboard switches: 12 for address mapping, one for SCON select, and three for general purpose use. The twelve address select switches map the 16-byte block containing the GCSR registers to one of 4096 possible locations within the 64KB VMEbus A16 space. The SCON switch enables the MVME188A system controller logic. The three remaining switches have user-defined functions; they can be read via an input port of the counter-timer. Holes are provided on the MVME188A system controller board for nine wire-wrap posts. These posts provide external connections for three of the four on-board timers. They also allow cascading of the timers and connection of alternate clock sources. Further information on these switches and timer connections is found in Chapter 2 in the section on Hardware Preparation.

16MB or 64MB DRAM Memory Board Functional

 Description Located in the middle of the MVME188A board set, the DRAM board has 144 locations for one megabit (or four megabit) memory chips providing storage of 16MB (or 64MB), with parity. The board set can be ordered with up to three additional memory boards (MVME288 series) to make a total of up to 64MB DRAM (or 256MB DRAM) maximum. Although the board packaging scheme limits MVME188A local DRAM to 64MB (or 256MB) using currently available chips, the DRAM boards decode and buffer the entire 4GB address range.

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