HIMA F2101 hydraulic servo system

Summary of Major Features • 32MB storage. 

• Single-bit error detection and correction. 

• Double-bit error detection. • Refresh cycles detect and correct single-bit errors. 

• DRAM implementation uses 4 megabit X 1 devices which allow operation with one dead memory device per bank. 

• Single-bit error counting. 

• Hardware diagnostic features allow planting and detection of bit errors. 

• Hardware diagnostic features allow syndrome field examination to pinpoint device failure. 

• Slave bus parity is monitored and error status is maintained. 

• Bus performance equal to parity-protected memory for the most frequently used cycles.

Error Detection and Correction 

As noted in the introduction, there are two memory banks, each with an Am29C660 error detection and correction circuit {EDq. The Am29C660 contains the logic necessary to generate check bits on a 32-bit data field according to a modified Hamming Code, and to correct the data word when check bits are supplied. Operating on data read from memory, the Am29C660 detects and corrects all single-bit errors and detects all double- and some triple-bit errors. For 32-bit words, seven check bits are used. Data items which have single-bit errors are corrected by the EDC and passed on to the MVME188A local bus {slave bus). The corrected data is also written back to the DRAM by hardware control. Multiple-bit errors which are detected by the EDC generate a bus error on the slave bus. Status is set indicating the source of the error and the yellow MEM ERROR LED is turned on. Data parity is generated when the data is passed to the slave bus. Parity is also checked when data is written to the memory.

Refresh Scrubbing

 The 32MB of memory is examined by the refresh logic every 63 seconds. Singlebit errors are corrected and written back to DRAM. Multiple-bit errors are ignored. Single-bit errors encountered during refresh are counted by the error counter. Hardware Diagnostic Features and Operating Modes This section describes operating modes and other hardware diagnostic features. Mode Selection Modes are selected via the CSR. Normal Mode The normal mode is set by writing a 00 to CSR bits 2 and 1. Single-bit error detection/correction, double error detection, refresh scrubbing, parity error detection, and error counting are enabled in this mode.

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