HIMA F2201 controller

ECNT[7 .. 0] represent the contents of the error counter. ECNT counts all single-bit errors that are encountered. The errors can be a result of refresh or bus access. Multiple-bit errors are not counted. The ECNT bits are reset to 0 and cleared by control and status register bit 3.SEV[6 .. 0] access the syndrome storage latch of the even bank of memory. The control of this field is the same as the syndrome bits for the odd field. OVF, the overflow bit, indicates the error counter exceeded the count of 255. It is reset to 0 and is read only, cleared by bit 3. Note that the OVF indicator is passed through the syndrome latch. Therefore, the CSR must be polled twice to get accurate OVF status (because the latch may have saved the single-bit error syndrome information before the error counter reached a terminal count). Also, a memory reference to the board must occur between the two reads of the CSR so that the syndrome latch is updated.

SPE[3 .. O] set to a 1 indicates that a bus parity error occured. 

The parity error was ether generated by the processor board or data/noise was clocked into the bus register on the ECC board. The system is not notified if this condition is detected. These bits must be polled or examined after a malfunction has been detected. They are cleared to zero by a power-on reset. Bits 4 thru 7 are also cleared by writing a 1 to bit 5. Bit 4 is for the least significant byte (highest address) and bit 7 is for the most significant byte. CCLR: writing CCLR to a 1 will clear the ECNT field and OVF bit. Reading CCLR indicates the status of the board-level state machine. This state machine is implemented with three separate sequencer circuits. If a malfunction occurs and the seperate circuits are not synchronized, CCLR will be set to a 0. A 0 is the error condition

Module Functional Description 

The main logic board on the right of the MVME188A board set contains three female, 100-pin miniature Rib-Cage connectors which mate with male connectors on the mezzanine module. The connectors serve both as a mechanical mounting and to provide paths for the CMMU memory bus (M bus). Also contained on the main logic board are the buffers, latches, decoders, and control logic required for the S bus, and a VMEbus interface

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