HIMA F3102 Control card

The MVME188A family realizes the computing power of the MC88100 RISC microprocessor and the MC88200 or MC88204 Cache/Memory Management Unit (CMMU) using a mezzanine board called a HYPERmodule which has one or more extremely fast CPU clusters. Each cluster has a single CPU and from 32KB to 512KB of cache memory. All modules run at 25 MHz.HYPERmodules measure only 3.5 inches by 8.5 inches (89 mm x 216 mm). They are made using the latest techniques in miniature packaging and printed circuit board manufacturing, adding high quality and reliability to match their performance. A HYPERmodule connects to the main logic board via a multiplexed M bus interface which has been enhanced with additional signals to support multiple CPU clusters, multiple CMMUs, fault checking modes, and HYPERmodule factory testing. (This is sometimes referred to as the Enhanced M Bus.)

M Bus Address Decoder 

The complex states of the multiplexed M bus are closely followed by an SRAM address decoder that determines which resource is the current M bus slave. Rather than configured through the use of switches or jumpers, the volatile SRAM is initialized by a local CPU running out of the ROM on the system controller board. This readily supports the various CPU cluster configurations on the mezzanine module and the address space assignments required by an application. The SRAM M bus address decoder can map any 4MB segment of M bus address space to utility space (local SRAM, ROM, control registers, etc), DRAM space (local memory boards), VMEbus A32 address space, or VMEbus A24 address space. 

Within the 4MB utility address space

 hardware reserves a ZMB space for ROM, a lMB space for SRAM, and lMB of CPU address space divided into three parts: CMMU register space, a block for the local control/status registers, and the VMEbus A16 short 1/0 address space. Because the CMMU chips require a lMB space at the top of memory, the top 4MB of M bus space must be mapped to utility space. A power-on reset causes the entire M bus address space to be mapped to the utility address space, which enables the initial bootstrap sequences to be fetched from ROM

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