Cache Coherency The CMMU chips support a cache coherency protocol in the respect that all eight caches contain a coherent image of their shared RAM on the M bus. For the fastest operation, it is suggested that the copy back mode be used to maintain the cache so that most writes are zero wait-state P bus accesses rather than multiple cycle M bus accesses. Random access memory on the DRAM module is coherent with the VMEbus. The SRAM VMEbus slave address decoder can be configured to request snooping on every VMEbus access of any MVME188A resource, and for the mezzanine module CMMUs to intervene when the local memory and local caches are not coherent.
Snooping is programmable on any 4MB
boundary in the VMEbus slave address decoder. It should be noted that the RISC complex is not coherent with the VMEbus; this requires, in ·systems with multiple masters on the VMEbus, that memory pages which must be accessed across the VMEbus be marked cache inhibit. So that an operating system kernel obtains strictly current device status and control information, J/O device registers must always be marked cache inhibit. While the VMEbus itself is not snooped, any VMEbus access to local memory may be snooped if that page is snoop-enabled in the VMEbus address decoder via the WV AD and RVAD registers.
M Bus Arbiter
So that processors on the global VMEbus are not held up by local accesses of DRAM, the VMEbus slave interface on the main logic board operates in the unfair mode when accessing the M bus. The M bus arbiter accommodates this by assigning highest priority to requests from the VMEbus, followed by code CMMUs 0 through 3 and data CMMUs 0 through 3 in descending order. To equally share M bus bandwidth, CMMU chips are programmed to operate in fairness mode. As an aid to developers of systems in which dual- and quad-processor versions of the MVME188A are used, a status register reports the CPU/CMMU configuration using the states of the M bus acknowledge lines. This permits the startup master to be selected by code in ROM.
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