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HIMA F3209 Embedded card

HIMA F3209 Embedded card

HIMA F3209 Embedded card

WHOAMI Register The WHOAMI register provides two pieces of information: the configuration of the HYPERmodule and the number of the CMMU that is current M bus master; it is unaffected by SRST or LRST. Bit assignments are shown in Table 4-35. There are six possible HYPERmodule configurations (twelve possible part numbers) built from three different base circuit boards. Three are fully stuffed versions, two are half populated versions, and one is a quarter populated version. The three PWB types are described in Table 4-32.

The write M bus address decoder register is used to set up the M bus physical address map. It is write only, and contains both the page address (upper data bits) and the code for the device to be mapped (lower data bits). Bit assignments are shown in Table 4-36. Although it is permissible to write to the WMAD register while the MADV bit is set in the CCSR, it is not recommended. The mapping change made by the WMAD write will take effect on the next M bus cycle.

RMAD Register

 The read M bus address decoder register is used to verify the configuration of the M bus physical address map. It is read/write; on read it returns both the page address (upper 10 data bits) and the code for the device mapped to that page (lower three data bits). On write, an address is written to the upper bits of the RMAD register; this address is used on a subsequent read as a page address. Bit assignments are shown in Table 4-37. The RMAD register is unaffected by SRST or LRST.On write, MPN[9:0] is supplied by the M bus master on data bits 31:22, and is written into the read M bus address decoder (RMAD) register. On read, the contents of the RMAD register are echoed in data bits 31:22. Note that the address decoder map is never modified by a write to this register (it is modified by writes to the WMAD · register). Unaffected by SRST or LRST.

WV AD Register 

The write VMEbus address decoder register is used to map portions of the local M bus space into the VMEbus address space(s) and to enable snooping of VMEbus accesses. Selected M bus resources can be mapped to respond to the following VMEbus address spaces: A24 only; A32 only; both A24 and A32; neither A24 nor A32 (all with or without snoop enable). WV AD is write only, and contains both the page address (upper 10 data bits), address space map select, and the codes for the space to be mapped (lower 2 data bits). Bit assignments are shown in Table 4-38. In a multi-CPU environment, only one CPU should be allowed control of the WV AD and RV AD registers. Refer to the caution under the RV AD register description.

                                                         

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