Similarly, the Universe ASIC supplies an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. The local reset driver is enabled even when the Universe ASIC is not system controller. Local resets may be generated by the RESET switch, a power-up reset, a watchdog timeout, a VMEbus SYSRESET∗, or a control bit in the MISC_CTL register.
The MVME2603/2604 front panel has ABORT and RESET switches and six LED (light-emitting diode) status indicators (CHS, BFL, CPU, PCI, FUS, SYS). The switches and LEDs are mounted on an LED mezzanine board that plugs into the base board.
Front Panel Indicators (DS1 – DS6)
There are six LEDs on the MVME2603/2604 front panel: CHS, BFL, CPU, PCI, FUS, and SYS.
❏ CHS (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME2603/2604. Lights when a halt condition from the processor is detected.
❏ BFL (DS2, yellow). Board Failure; lights when the BRDFAIL∗ signal line is active.
❏ CPU (DS3, green). CPU activity; lights when the DBB∗ (Data Bus Busy) signal line on the processor bus is active.
❏ PCI (DS4, green). PCI activity; lights when the IRDY∗ (Initiator Ready) signal line on the PCI bus is active. This indicates that the PCI mezzanine (if installed) is active.
❏ FUS (DS5, green). Fuse OK; lights when +5V DC, +12V DC, and
–12V DC power is available from the base board to the transition
module and remote devices.
Memory Maps 2
There are three points of view for memory maps:
❏ The mapping of all resources as viewed by the processor (MPU bus memory map)
❏ The mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map)
❏ The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map) The following sections give a general description of the MVME2603/2604 memory organization from the above three points of view. Detailed memory maps can be found in the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation
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