ICS TRIPLEX T3151 Channel contact module

The PIB supports seven DMA channels. Channels 0 through 3 support 8-bit DMA devices. Channels 5 through 7 are dedicated to 16-bit DMA devices. The channels are allocated as follows:The MVME2603/2604 SBC has eight potential sources of reset: 1. Power-on reset 2. RESET switch (resets the VMEbus when the MVME2603/2604 is system controller) 3. Watchdog timer Reset function controlled by the SGS-Thomson MK48T559 timekeeper device (resets the VMEbus when the MVME2603/2604 is system controller)4. ALT_RST∗ function controlled by the Port 92 register in the PIB (resets the VMEbus when the MVME2603/2604 is system controller) 5. PCI/ISA I/O Reset function controlled by the Clock Divisor register in the PIB 6. The VMEbus SYSRESET∗ signal 7. VMEbus Reset sources from the Universe ASIC (PCI/VME bus bridge controller): the System Software reset and Local Software Reset

Endian Issues 

The MVME2603/2604 supports both little-endian (for example, Windows NT) and big-endian (for example, AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME2603/2604 handles software and hardware differences in big- and little-endian operations. For further details on endian considerations, refer to the MVME2600 Series Single Board Computer Programmer’s Reference Guide, listed in Appendix D, Related Documentation.

Processor/Memory Domain 

The MPC603/604 processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the Falcon memory controller chip set, as well as DRAM, ROM/Flash, and system registers, always appear as big-endian.

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