FOXBORO FCM10E P0914YM Overspeed detection module

The MVME167 provides a timeout function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by software for 8 µsec, 64 µsec, 256 µsec, or infinite. The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer.There are two points of view for memory maps: 1. Local bus memory map – The mapping of all resources as viewed by local bus masters 2. VMEbus memory map – The mapping of onboard resources as viewed by VMEbus masters

Local Bus Memory Map 

The local bus memory map is split into different address spaces by the transfer type (TT) signals. The local resources respond to the normal access and interrupt acknowledge codes. Normal Address Range The memory map of devices that respond to the normal address range is shown in the following tables. The normal address range is defined by the Transfer Type (TT) signals on the local bus. ❏ On the MVME167, Transfer Types 0, 1, and 2 define the normal address range.

For a complete description of the register bits,

refer to the Single Board Computers Programmer's Reference Guide or to the data sheet for the specific chip. 2. On the MVME167 this area does not return an acknowledge signal. If the local bus timer on the MVME167 is enabled, the access times out and is terminated by a TEA signal. 3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits. 4. This area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 5. This area does return an acknowledge signal.

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