This register defines which bits of the Translation Address are significant. A logical one "1" indicates significant address bits, logical zero "0" is nonsignificant. The non-significant bits will come from the VMEbus address that accesses the local resource. Normally, MS bits will be set, down to the size of memory to be accessed.Defines the access restriction for the address space defined with this slave address decoder. Default is $03FF. See description of VMEchip2 bits in Single Board Computer Programmer’s Reference Guide Ending address of the local resource that is accessible by the VMEbus, as viewed by the VMEbus.
Disk/Tape Controller Modules Supported
The following VMEbus disk/tape controller modules are supported by the 167Bug. The default address for each controller type is First Address and the controller can be addressed by First CLUN during commands BH, BO, or IOP, or during TRAP #15 calls .DSKRD or .DSKWR. Note that if another controller of the same type is used, the second one must have its address changed by its onboard jumpers and/or switches, so that it matches Second Address and can be called up by Second CLUN.
Network Controller Modules Supported
The following VMEbus network controller modules supported by MVME167Bug are shown in Table C-1. The default address for each type and position is shown to indicate where the controller must reside to be supported by MVME167Bug.
❏ Try these simple troubleshooting steps before calling for help or sending your CPU board back for repair.
❏ Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.)
❏ Selftest may not run in all user-customized environments
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