TRICONEX 3351 Displacement speed clamp

The user interface of the Intelligent Counter/Controller is implemented by a 15 MHz 68HC000 CPU supported by 64 Kbyte of EPROM firmware, 128 Kbyte of zero-wait-state static RAM, and highly-integrated control and interrupt logic. The VMEbus host programs the ICC by queueing function control blocks in local memory and issuing commands. The CPU responds to the commands by interpreting the function control blocks, configuring the system timing controllers, and then acknowledging the host command. Once configured, the CPU maintains data structures of measurement data in local memory and interrupts the VMEbus host when a measurement or control process is complete.

The slave VMEbus interface of the VMIVME-2540 

locates the 64 Kbyte VMEbus local memory window in A32 or A24 address space with DIP switches, with nonprivileged and/or Supervisory access. The VMEbus host must arbitrate with the 68HC000 CPU for local bus access since the RAM is shared. The data accesses may be D32, D24, D16, and D08, and unaligned transfers are supported. Because the local CPU executes its code from RAM, the arbiter relinquishes control of the local resources after a single VMEbus data transfer.

The Intelligent Counter/Controller

 supports two VMEbus interrupter modules which may assert any of two IRQ levels simultaneously. When serviced, the interrupter modules respond with an 8-bit interrupt vector and automatically clear the pending IRQ. The CPU maintains a queue of pending interrupt events in memory, writing a new IRQ to the interrupter modules when the previous event is cleared.

Pulse-Width Resolution (for Nonsquare Wave): 131 s to 13.1 ms: 0.015 percent maximum 13.1 ms to 200 ns: Percent Error = 100* (200 ns/Pulse Width)

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