TRICONEX 4108 Sequence control module

Each interrupt input has its own associated Vector Register, see Table 4.9-2. Each register is eight bits wide and supplies a data byte during its interrupt acknowledge cycle if the associated External/Internal (X/IN) Control Register bit is clear ("zero"). This data can be status, identification, or address information depending on system usage. The information is programmed by the system user.When the MC68153 is reset, the registers are set to a known condition. The Control Registers are set to all "zeros" (low). The Vector Registers are set to $0F. This value is the MC68000 vector for an uninitialized interrupt vector.

THE COMMAND REGISTER DEFINITION (06H)

 The VMIVME-5576 may generate an interrupt in any or all other chassis through the use of the Command Register. Valid choices for interrupts are: 1,2,3. Table 4.6-1 shows all combinations possible. The interrupts are processed just like data so all words sent previous to the interrupt command will be present on receiving board’s memory before the interrupt will be issued to the receiving board. The Command Register is Write only.

In the event of an external interrupt (i.e., int1, int2, int3)

 the VMIVME-5576 will prevent the loss of any subsequent interrupt of the same type through the use of a dedicated FIFO for each interrupt type. The interrupt handler must execute a Read of the sender ID Register in order to allow the next interrupt of the same type to be sent to the BIM. An example is that an interrupt int1 has been sent across the link immediately followed by a second int1. The receiving node must determine that the VMIVME-5576 has issued a int1 through the use of the resulting VME int level (0 through 7) and its vector. The second interrupt will remain in the int1 FIFO until the receiving node executes a Read of location 26 HEX which will allow the second interrupt int1 to be issued to the BIM. This method guarantees that all interrupts sent on the link will be serviced and the receiver knows the ID of the node which sent the interrupt it is currently servicing. Only one Read per interrupt is allowed, otherwise loss of subsequent interrupts may occur.

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